In prior production integrated circuits, such as microprocessors, frequencies have been in the 100-400 megahertz (MHz) range. In general, those processors are densely populated by logic and memory devices, and there is little spare area available for other functions, e.g., decoupling capacitors. Prior art decoupling capacitors are implemented as Metal-Insulator-Semiconductor (MIS) structures integral to the silicon bulk, as described by Grzyb in U.S. Pat. No. 5,656,834. Historically, in the pre-gigahertz regime, MIS capacitors are added to dataflows as an afterthought, using whatever spare area is available after the main logic design is complete, wherever that spare area happens to be.
This haphazard historical approach to decoupling capacitance is sufficient for stabilizing the power supply voltage, Vdd, when the processor frequency is less than a few hundred MHz. In future designs done in the gigahertz (GHz) regime and beyond, more decoupling capacitance will be needed, and the proximity of that capacitance to the devices that are switching is much more important. That is, in the GHz regime, a haphazard approach to capacitance is not acceptable: a relatively high capacitance is required, and it must be present in a proximate and regular way throughout the logic and memory dataflows.
From a power perspective, an ideal IC would use 100% of its area for decoupling capacitance and current distribution, and none of its area for logic or memory. From a logic and memory perspective, an ideal IC would have 100% of its area used for logic and memory, and no area spent on the overhead of capacitors, which serve no function insofar as computation goes. In U.S. Pat. No. 5,366,931, Kim attempts to satisfy this contradiction using a structure in which the entire back side of the chip is used for decoupling capacitance.